SELF TESTING RISC PROCESSOR USING JTAG

Abstract

Modern technologies are built to solve complicated issues in real time and it seems like the IC only includes the circuitry for the dedicated logic but there is some circuitry that is added which is equally important which we called testing circuitry. This kind of circuits are basically used to test the IC in less time and fabrication process. All the work, comes under the profile DFT (Design for Testability). DFT also works on making a design, a self-testing design because there are many devices in the field which needs to be test after a particular time regularly like radar system of automobiles. The pros of DFT is that it eases the testing process of a design in general but the cons are that because of the logic, hardware requirement increase which leads to rise in two factors on which whole VLSI industry focusing on: Area and Power. The DFT logic increase these two factors which is not preferable but there is a trade-off between testing time, area and power because the end goal is to get a efficient device in less price. This project is focused on providing a basic knowledge about Design for Testability (DFT). Then, we are going to implement same methodology studied in RISC processor and make it a self-testing processor. At last, we also going to study the implement design in AMD Xilinx VIVADO 2020.2 and perform a power analysis on the basis of which we will conclude the result.