A 12-Bit 1.2-GS/s CURRENT-STEERING DAC in 45-nm CMOS TECHNOLOGY

Abstract

This research paper presents a 12-bit 8-4 segmented current-steering DAC (Digital-to-analog converter) that offers notable advantages, particularly in terms of its reduced power consumption compared to other similar designs. The exceptional performance of our DAC can be attributed to two key factors: the use of a thermometer encoder and efficient digital input bit segmentation. These features contribute to enhanced precision and reduced power requirements, setting our DAC apart from existing solutions in the field. DACs are the essential component that bridge gap between the advancing methods of digital signal processing and analog signal transmission in advance communication systems. A 8-4 segmented current steering architecture is proposed where 8 most significant bits (MSB) are implemented using thermometer encoded current cell array while 4 least significant bits (LSB) are implemented using binary weighted current cell architecture. Major sub-components of circuit involve inverter, logic gates for binary -to thermometer encoder, latch, switch driver and multiple current sources. The designing and simulation of the circuit is done using Cadence Virtuoso and Power Dissipation is compared with other existing DAC designs in literature.These enhancements significantly reduce glitches and improve the accuracy of the DAC's output.DAC dissipates a total power of about 44.95 mW when running at a sample rate of 1.2 GHz with CMOS technology of 45nm. While the supply input voltage is held constant at 1.2 V, the DAC’s digital input is pulsating in nature in which the ON voltage is 1V and OFF voltage is 0V. Also, the DAC has a spurious-free dynamic range (SFDR) of 41.77 dB .