ROUTER 1x3 RTL DESIGN PACKET BASED PROTOCOL USING VERILOG HDL

Abstract

Routers forward data packets between computer networks. It is a routing device at OSI Layer 3. It uses the address field in the packet header to direct an incoming packet to an output channel. Routing allows communications to travel from one computer to another and ultimately reach the target device by shifting data packets traveling from one place to another Routers are networking devices that route data packets across computer networks. Unlike a network switch, which joins data lines from server l networks, it is connected to two or more data lines from separate networks. This focuses mostly on the study of the router device, its top level architecture, and the synthesizing, simulating, and connecting of its many sub-modules, such as Register, FIFO, FSM, and Synchronizer, to its top module. Sending and receiving packets through routing The IP address of the destination network packet determines how the packet is routed and passed either one of the results ports to the input port. An error detection method called parity checking verifies the integrity of digital data transferred between server and client device networks. By using this method, data transmitted from the server network device to the client network device is guaranteed to arrive undamaged. It is an active low synchronous IP that, upon performing specific tasks, causes the router to reset. Under test conditions, the router FIFOs are empty, and the low valid output signals imply that no valid packets have been found on the output data bus. Existing methodology High Power 1x3 router In order to route data in a network that is using a lot of power due to the use of switches and bridges between various devices, switches and routers are the only essential components of a successful network and architecture. Clocking gates are not used in this high power 1x3 router since it increases dynamic power dissipation. Proposed methodology A router is a basic hardware device that uses a network to transport data packets from one place to another. It is situated at gateways, which are the locations where two or more networks converge, and is connected to a minimum of two networks, usually two LANs or WANs, or a LAN and the network of its ISP. It is an OSI routing device at layer 3. v Based on the length of the incoming packet and the IP address elements in the packet header, it sends the packet to an output network. Routing is the process of moving a data packet from a source to a destination, enabling messages to move between computers until they arrive at their intended destination. A router is a networking device for computers that makes it easier for data packets to move between networks. Unlike a network switch, which links data lines from several networks together, it has two or more data lines from different networks connected to it. This research examines both the synthesis and top-level layout of the network device, simulation, and coupling of the Synchronizer and sub-modules such as FIFO, FSM, and Register are sent to the top module. Three output ports are available for sending the packet. The package is divided into three sections. The three components are the header, the data, and the frame check sequence. The length of the packet to be transmitted may vary from 1 to 63 bytes, with an 8-bit packet width. Packets are directed to the correct ports via the switch based on their intended addresses. Each output has an own eight-bit port address. If the intended recipient address and port address of the packet match, the switch transmits it to the output port. It has an 8-bit data length. In this proposed research, synthesis and simulation are performed using the Xilinx ISE IDE Tool. Because there are fewer states in the FSM in the suggested architecture, it takes less time to produce a response, which clearly improves frequency.