LOW POWER ISOLATED READ PORT SRAM CELL DESIGN IN 45nm WITH LECTOR TECHNIQUE

Abstract

This project aims to reduce leakage power consumption on SRAM. We have implemented LECTOR technique in 9T SRAM. The leakage power has a substantial improvement because of LECTOR technique. We observed 26% reduction of leakage power compared to 9T SRAM but delay of read and write have been affected because the signals are not good (LECTOR transistors are in cutoff region), which leads to increase in rise and fall delay. Further, this project compares stability and power consumption of different types of SRAM cells like 6 T, 8 T, 9 T. This project aims to find the parameters of these cells and compare them. Comparison is done specifically stability and power consumption and related parameters like Read stability, write stability, hold stability by finding out noise margins with butterfly curve. This project also aims to find out power dissipation of these cells. Static power dissipation and dynamic power dissipation are measured. Finally, write delay and read delay of these structures are also obtained. Main motivation of this project is to improve these parameters as leakage power dissipation is very important because it contributes largest proportion of power consumption in recent nanometer CMOS devices. This project observes considerably improvement in leakage power by using different structures and different structures leads to improvement in static noise margin. To reduce leakage power consumption on SRAM we have implemented LECTOR technique in 9T SRAM. The leakage power has a substantial improvement because of LECTOR technique. We observed 26% reduction of leakage power compared to 9T SRAM but delay of read and write have been affected because the signals aren't good (LECTOR transistors are in cutoff region) which leads to increase in rise and fall delay.