A LOW POWER AND LEAKAGE REDUCTION TECHNIQUE FOR CMOS USING CASCADE LEAKAGE TRANSISTOR

Abstract

In the realm of nanometer-scale CMOS technology, minimizing power consumption and leakage currents is essential for enhancing the energy efficiency of modern electronic devices. This dissertation presents a novel approach to reducing power and leakage through the development of the cascade leakage transistor (CLT) technique. The CLT method integrates advanced low-leakage strategies with the cmos technique, specifically applied to CMOS inverter design and other universal gates at the 45 nm in cadence software. The CLT technique involves utilizing two cascade leakage transistors to control the on and off states of the P-type pull-up and N-type pull-down transistors in a CMOS inverter and other universal gates. This innovative configuration effectively reduces static leakage power dissipation while preserving the integrity of the output signal waveform. Due to the cascade arrangement Despite an increase in propagation delay compared to conventional CMOS inverters, the trade-off results in a substantial leakage power reduction of approximately 59% and total power dissipation reduced by 24% overall for not gate compared to other technique.