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dc.contributor.authorSINGH, BHARGAV-
dc.date.accessioned2024-08-05T08:45:14Z-
dc.date.available2024-08-05T08:45:14Z-
dc.date.issued2024-05-
dc.identifier.urihttp://dspace.dtu.ac.in:8080/jspui/handle/repository/20744-
dc.description.abstractIn this project, a Combinational circuits based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. This goal of this thesis Carbon Nano tube Field Effect Transistors (CNTFETs) based design using Dynamic Gate Diffusion Input( D-GDI) ,Using the proposed approach, the combinational logic circuits such as XOR , XNOR gates and MUX are implemented which results in a full-swing, Proposed full-adder cell in the CNFET technology. The proposed circuits For the designing and simulation of circuit purpose we have used Stanford CNTEFT model Verilog A with 32nm technology parameters.The design tool used for the simulation is Cadence Virtuoso Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder, half subtractor , encoder circuit. The recommended Dynamic GDI technique appears to consume 28% less power than the standard approach, based on the data.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesTD-7257;-
dc.subjectCADENCE VIRTUOSOen_US
dc.subjectCMOSen_US
dc.subjectP-CNTen_US
dc.subjectN-CNTen_US
dc.subjectCNTFETen_US
dc.subjectSWCNTen_US
dc.subjectMWCNTen_US
dc.subjectDGDIen_US
dc.titleCNTFET BASED DYNAMIC GDI COMBINATIONAL LOGIC CIRCUITSen_US
dc.typeThesisen_US
Appears in Collections:M.E./M.Tech. Electronics & Communication Engineering

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