Please use this identifier to cite or link to this item:
http://dspace.dtu.ac.in:8080/jspui/handle/repository/20744
Title: | CNTFET BASED DYNAMIC GDI COMBINATIONAL LOGIC CIRCUITS |
Authors: | SINGH, BHARGAV |
Keywords: | CADENCE VIRTUOSO CMOS P-CNT N-CNT CNTFET SWCNT MWCNT DGDI |
Issue Date: | May-2024 |
Series/Report no.: | TD-7257; |
Abstract: | In this project, a Combinational circuits based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. This goal of this thesis Carbon Nano tube Field Effect Transistors (CNTFETs) based design using Dynamic Gate Diffusion Input( D-GDI) ,Using the proposed approach, the combinational logic circuits such as XOR , XNOR gates and MUX are implemented which results in a full-swing, Proposed full-adder cell in the CNFET technology. The proposed circuits For the designing and simulation of circuit purpose we have used Stanford CNTEFT model Verilog A with 32nm technology parameters.The design tool used for the simulation is Cadence Virtuoso Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder, half subtractor , encoder circuit. The recommended Dynamic GDI technique appears to consume 28% less power than the standard approach, based on the data. |
URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/20744 |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
BHARGAV SINGH M.Tech.pdf | 2.53 MB | Adobe PDF | View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.