DESIGN AND IMPLEMENTATION OF A 10T SRAM CELL UTILIZING LOW POWER TECHNIQUE

Abstract

As technology advances, several improvements are being demanded from cache memories and in turn from the SRAM cell with regards to certain aspects such as stability, access speed, power consumption, etc. A 10T SRAM cell architecture is proposed, which is enhanced with respect to the aspects mentioned above. According to the simulation findings, it is established that the proposed model has lower power consumption (i.e., 51.7nw) compared to the 10T SRAM cell (i.e., 65.14nw). The analysis associated depicts that the read latency of the proposed model is 110.9ps, which is lower than the 10T SRAM cell(i.e., 165.6ps). All the simulations were performed using Cadence Virtuoso software, operating at 1 volt, with 45 nm CMOS process technology. The proposed 10T SRAM cell has better performance and low power consumption than the compared design.