DESIGN OF LOW LEAKAGE SRAM CELLS WITH ENHANCED STABILITY FOR NEAR THRESHOLD VOLTAGE REGIME

Abstract

Operating the SRAM cell at near-threshold voltages is an effective way to achieve higher energy efficiency though it reduces stability and degrades the cell’s performance. This thesis presents novel SRAM cells designs characterized by high hold, read stability along with enhanced writability (HSNM/RSNM/WSNM) as well as low leakage power. The proposed devices employ additional read buffer circuitry that eliminates read disturbance issue by decoupling the read path from internal data storage nodes. The feedback-cutting and power-gating based write assist techniques respectively disrupt the internal feedback during read cycle thereby facilitating a smoother write operation. The core circuit of the SRAM cells has been augmented by Schmitt trigger and tristate inverters which enhance hold stability and reduce the leakage power dissipated. The simulation results in 90nm CMOS technology at a supply voltage of 0.5V show that the proposed devices outperform conventional 6T SRAM cell showing 41%/ 297.72%/ 27.2% and 22.62%/ 281.81%/ 12.84% increase in HSNM/RSNM/WSNM respectively. Moreover, the presented designs drastically reduce leakage power dissipation as compared to peers showing as high as 3.45x reduction.