DESIGNING OF 32-BIT RISC V ARCHITECTURE

Abstract

The University of California, Berkeley developed the RISC-V instruction set architecture. The RISC architecture was conceived because most CPU instructions were not utilized by the majority of computer programs. The RISC-V processor aims to reduce the instruction set and increase the utilization of register resources. Its open source and free nature has garnered the interest of many IT giants and startups. "RISC" stands for "Reduced Instruction Set Computer," which refers to executing a smaller set of computer instructions, and "V" signifies the fifth generation. It is an open- source Instruction Set Architecture (ISA) based on the well-established RISC principles. We designed a processor that supports 32-bit instructions, propagating through five pipeline stages: fetch, decode, execute, memory access, and writeback. We also demonstrated the interconnection of instruction and data memory with the CPU core, forming a complete processor. Pipelining enables the simultaneous execution of multiple instructions and illustrates the processing of an instruction using data from source and destination registers. Additionally, we addressed the data hazard issuewhere upcoming instructions require updated register values from previous instructions. This was managed through stalling, which gives an extra cycle to wait, and a forwarding unit, which directly passes data to the next instruction, speeding up the process and ensuring correct values. To evaluate the processor's functionality, we used the Fibonacci program and confirmed successful memory storage of the series. Consequently, various manufacturing firms have announced support for RISC-V with open-source operating systems. This new architecture is available under open, liberal, and free licenses, receiving significant backing from the chip and device manufacturing industries. It is designed to be flexibly expandable and configurable for various applications. Professor David Patterson at the University of California, Berkeley, created the RISC architecture in the 1980s. Professors John Hennessy and David Patterson contributed to the field through their works "Computer Organization and Design" and "Computer Architecture at Stanford University," respectively, earning them the ACM A.M. Turing Prize in 2017.