CNTFET BASED DESIGN OF TERNARY ADDERS BASED ON GDI TECHNIQUE

Abstract

This study illustrates the design of ternary logic gates, half adders (HA) using CNTFETs, and the Gate Diffusion Input Technique (GDI). The scaling down of devices is increasing which leads to various issues in the device. We know, the dimension of devices has been decreased by two in every two years (According to Moore’s) and this scaling down of devices facing several drawbacks. Nonetheless, as the ITRS 2009 edition points out, as device dimensions have decreased to the approximately 22-nm region, scaling down is encountering constraints pertaining to device performances and manufacturing technologies. This scaling down is causing problems for the devices, like passive power dissipation, changes in device structure and doping, including electron tunneling via thin insulator layers and narrow channels, as well as associated leakage currents. By changing the channel materials in most structures and substituting carbon nanotubes or arrays of carbon nanotubes, we can get around these restrictions. So, in the designing of the gates we will use CNTFET model instead of MOSFET. We all have learnt about binary logic but in our designing, we will use ternary logic as it is three valued and has more advantages over binary logic in the design of digital system. Now we can transmit more data with minimal interconnections results in less memory requirements. Because of the less estimation interconnection cost it receives more attention than others. To implement the design, we can use HSPICE or Cadence by taking model file compatible with these tools. On the Stanford University CNFET Model, the CNTFET model file is accessible. Semiconducting single-walled carbon nanotubes function as the channels in this tiny, SPICE-compatible model that represents unipolar MOSFETs working in enhancement mode... Thus, we employed this model in our project. When compared to traditional binary logic design gate techniques, this ternary logic with CNTFET design technique offers superior speed and power consumption. As a result, the power delay product is reduced. It has been noted that, in comparison to the current design, the suggested HA design's delay has been significantly reduced. In this study, the design has been covered in further detail. The device used for this simulation is cadence virtuoso.