STUDY AND IMPLEMENTATION OF POWER REDUCTION TECHNIQUES IN COMPLEX CIRCUIT

Abstract

The sensing amplifier has become the focal point of memories and peripheral circuits. The increasing need for portable devices has posed a significant challenge for high-speed memories in terms of achieving longer battery life. SRAM, also known as static random-access memory, performs a crucial function in achieving lesser power and faster in performance in the era of digital technology and VLSI circuits. The present trend of nanoscale devices has caused an increase in sub-threshold leakage current in VLSI circuits. This is due to the continuous lowering in the threshold voltage and the thinning of the gate oxide, which enhances tunnelling leakage current and poses a problem. Reducing power consumption enhances the reliability and efficiency of a device. Consequently, CMOS innovation emerged as the most favoured choice for devices that require low power consumption. Therefore, leakage power reduction techniques have become a necessity for sustainment of this scaling in the VLSI circuits. Memories created using CMOS includes sensing amplifiers. The stored data are retrieved via Sensing Amplifiers. The sensing amplifier (SA), which plays a critical role in the read circuitry of volatile and non-volatile memories, including FLASH, has a substantial impact on memory performance. The four main performance parameters for SA are physical footprint, power utilization, energy consumption, and access time. This thesis presents a redesigned design of a sense amplifier that incorporates several power reduction approaches into the "Conventional Charged Sense Amplifier (CSA)". The charged sense amplifier (CSA) is an essential element of SRAM and memory systems. In one of the publications, improved CSA has been proposed by implementing the Stacked transistor approach for leakage power reduction. Taking inspiration from the same, other conventional leakage power reduction techniques namely Galeor, Lector, Sleep transistor, Sleepy Keeper have been integrated in CSA. Apart v from leakage current reduction techniques, some of the other power reduction techniques proposed in different publications namely SAPON, Drain Gating, ECRL(Adiabatic), Isolated Sleepy keeper have been applied to the CSA. Their transient analysis has been done and a comparative study of power dissipated in each configuration has been presented. The different configurations of CSA have been proposed and compared in this thesis, with each one being explained in some detail. The simulations have been carried out in LTSpice in 45 nm technology node and 1V power supply. The power is calculated at 0.9V for all the configurations. All the power reduction techniques have shown promising results, however some like SAPON and Sleepy keeper have led to extraordinary power reduction. As far as adiabatic techniques are concerned, only ECRL was analyzed as the area compensation is very large in Adiabatic techniques and has the potential to overshadow the power reduction benefits.