CHAOS BASED BIST DESIGN FOR TESTING OF DIGITAL CIRCUITS

Abstract

Due to the increasing design size and complexity of recent VLSI design Circuits (IC) and the decreasing time-to-market, testing is one amongst the key bottlenecks within the IC design and development cycle. Nowadays, in semiconductor industry technique for testing has been serious concern. A not well-designed testing technique, of any chip would be a harmful for design engineering as well as for verification engineer in many ways like cost, effort and consumer’s trust. So now-a-days there is one promising technique for testing of design which is speedily changing with the developments in technology as size of device reduces which is BIST. As a result of small size device, hardware is also becoming complicated, this tendency has shifted to incorporate BISTs in electronic equipments which required high performances for offline testing. In BIST we test a design with the help of pattern generator, output response analyzer and with controller to manage all the actions of testing. Also, a comparison has been made between ‘Linear Feedback Shift Register’ (LFSR) based and chaotic circuit based BIST using hardware utilization and timing parameters. This report presents the testing of circuit for a BIST functioning in testing mode of operation. For simulations and synthesis, VCS and Verdi synopsis tools for Verilog and MATLAB/SIMULINK has been used. The output waveforms of chua’s circuit and MISR/SISR are plotted.