COMPARATIVES ANALYSIS OF RING OSCILLATOR FOR LOW POWER APPLICATION

Abstract

VLSI is an evergreen field that is constantly expanding. To fit more gates on a given chip area, a significant amount of work is required. As a result, removing the heat generated is difficult. Using low-power circuits, this problem can be solved. In the time being computerized industry, a low power requirement has become primary goal. In the design of VLSI chips, power draining has becomes as critical as performance and size. Low-power chip requirements are becoming increasingly important in the VLSI business as chip dimensions shrink and environmental issues become more important. Because of the requirement to low package cost and increase battery life, power optimization is as critical as time for many systems. In the past, the total power dissipation of CMOS devices was dominated by dynamic power. This thesis discusses CMOS, lector, forced NMOS, forced 2 NMOS, forced PMOS as approaches for reducing power requirements at various stages of CMOS architecture. The results are examined at various supply voltages while maintaining the load capacitance (Cload = 500fF) which include power, delay, switching threshold voltage, noise margin, the inverter utilizing forced NMOS technology is considered good because the noise margin obtained is the highest here, 2.48V evaluated at 4.02V supply voltage. When all other factors are equal, the inverter adopting the lector approach consumes less power than the other inverters at all supply voltages. This thesis approaches with the design and exploration of the frequency of ring oscillators using the CMOS 45nm, 32nm, 22nm in a Symica simulation tool. A Ring Oscillator is an effectual device incorporated of an odd number of NOT gates and its output runs between two levels of power standing up and down. There are many challenges forth while framing a CMOS ring oscillator that can be delay, sound, and glitches. CMOS is the technology of choice for several applications, low-power CMOS oscillators are in high demand. The frequency of a CMOS ring oscillator was measured using waveform time zones for five, seven, and nine phases. This aids in the comparison of ring oscillators at various technology nodes and it is observed that the frequency is found to be maximum at a five-stage ring oscillator in each case i.e. 12.97GHz at 45 nm, 8.25GHz at 32 nm, 4.74GHz at 22 nm. Further, the designing of the ring oscillator is done to keep down the power consumption of the circuit while making the other parameters like the dimensions of the v transistors constant i.e. width and length of transistor at 45nm technology. The proposed designs of the ring oscillator are sleepy stack ring oscillator, forced NMOS ring oscillator, forced 2 NMOS ring oscillator, forced PMOS ring oscillator, lector ring oscillator, forced stack ring oscillator. Simulations of these circuits show that as the value of VDD increases the current across the circuit increases and as the value of current rise, the power of the ring oscillators shoot up. The power consumption of forced stack, lector, forced NMOS, forced PMOS, sleepy stack, forced 2 NMOS ring oscillators at 0.2V are 0.0216µW, 0.0348µW, 0.021µW, 0.044µW, 0.03µW, 0.129µW, 0.134µW.