MEMRISTOR BASED MEMORY DESIGN

Abstract

Since the past few decades, SRAM is preferred in portable devices and it makes up a large portion of a system-on-chip area. Despite the fact that it is fast, the volatile nature limits its applications. Moreover, the continuous downscaling in technology and supply voltage encounters serious issues in device performance such as higher leakage power consumption. To overcome such issues, the researchers and academia have come up with a solution which is introduction of non-volatile memory (NVM) device with SRAM known as nvSRAM. The NVM device is generally used to back up the information in SRAM when supply voltage is turned off. Further, NVM devices can suppress leakage power consumption by turning off supply voltage of infrequently used SRAMs without loss of information. Among the different types of NVM, memristor have certain benefits such as small size, high-speed of operation, low programming voltage and compatibility with CMOS manufacturing process. The 6T2R cell is the most common nvSRAM cell. However, it suffers with leakage issue due to the direct connection of memristor with internal nodes. To overcome this, various methods are suggested in literature. The commonly used approach is isolating memristor with internal nodes through a control transistor. Other than this, different techniques to improve nvSRAM performances like margin, power consumption, store/restore functionality are introduced in the existing work. In most of the existing nvSRAM cells, differential write operation is performed. It needs charging/discharging of bitline pair that contributes significant percentage in total power consumption. To reduce this, a nvSRAM design is introduced in this work that performs single ended write operation and reduces write power consumption in an extent. The v proposed design uses a feedback transistor to improve write operation. It also improves store/restore performance through 1T1M structure. The presence of feedback transistor causes increment in leakage power consumption; three different approaches are suggested to overcome this. To overcome write/read conflict, two nvSRAM designs with read decoupled (RD) port are introduced in this work. The isolation of read operation from internal nodes enhances read margin of the proposed designs. In one of the designs, the grounded gate low threshold voltage transistor is used to maintain the performance near threshold voltage. It also uses a charge pump circuit to overdrive read port to improve read performance. Another, proposed design uses column shared technique to improve write and restore performances. The 1T1M structure is used in both the designs to perform non-volatile operation. Other than margins and power consumption, delay is also an important parameter and less attention is paid in this direction. The longer store/restore delay values may lead to loss of data. For this, three different techniques to reduce store and restore delays are presented in this work. These techniques are generic and are applicable to nvSRAM cells which uses 1T1M configuration to perform non-volatile operation. The control signals values are altered in these approaches. For verification purpose, these techniques are applied on one of the proposed designs. Other than this, a transmission gate (TG) based nvSRAM design is also introduced in this work. In existing nvSRAM cell performing single ended write operation, the an NMOS transistor is used to access the data. As it passes strong ‘0’ and weak ‘1’, the write ‘1’ operation speed is degraded. To overcome this, the NMOS access transistor is replaced by TG that gives both strong ‘0’ and ‘1’ and leads to improved write performance. vi In this design, memristor is connected between internal node and read bitline through read pass transistor to perform non-volatile operation. The scaling in technology and supply voltage lead to degradation in nvSRAM cell performance due to increase in sensitivity to process variations. Hence, it is required to introduce process invariant nvSRAM cells. In this work, two process invariant nvSRAM designs are introduced. Both the designs use Schmitt Trigger (ST) inverters in the core instead of CMOS inverters. The ST inverter provides tolerance against process variations specially at lower voltages. Also, the RD port is used to perform read operation. In one of the designs, memristor is connected between internal node and read bitline line to perform non volatile operation. Another design uses 1T1M structure to perform non-volatile operation. Further, the failure probability analysis is carried out to examine the performance of both the proposed designs against process variations and Vmin values are observed through the analysis. In the thesis, the performances of proposed designs are analyzed through SPICE simulations and TiO2 based memristor model is used to perform non-volatile operation. The results of proposed designs are compared with the considered nvSRAM cells. The supply voltage variation study is also performed for completeness.