TCAD ANALYSIS AND MODELLING OF GATE STACK GATE-ALL AROUND JUNCTIONLESS NANOWIRE FIELD-EFFECT TRANSISTOR FOR SENSING APPLICATIONS

Abstract

Continuous market demand drives device engineers to create Integrated Circuits (ICs) with low power dissipation and low fabrication complexity. Nanoelectronics technology is approaching the atomic/physical device limits due to the increasing demands of semiconductor chips. Significant technological development has been in the integrated circuit industry over the past few decades. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a crucial Integrated Circuits (IC) component. The integrated circuit doubled the number of on-chip transistors every generation, reducing physical device size. It has attracted numerous novel structures and MOSFET devices. However, scaling presents numerous challenges as it approaches the nanometre regime. It causes threshold voltage roll-off, short channel effect (SCEs), increases body-bias impact, and other negative consequences. SiO2 gate oxides, in particular, have already reached a few atom lengths and thicknesses, resulting in increased power dissipation due to the quantum mechanical tunnelling effect. Therefore, new materials and novel device architectures are necessary to guarantee the final scaling in device dimensions and sustain the anticipated performance benefit from the scaling. One of the most promising device architectures for extending the scaling of the CMOS device is the Gate All Around (GAA) MOSFET, which provides better hot carrier reliability than the Bulk MOSFET due to improved gate control and the best electrostatic control of the channel. Serious challenges with the device and circuit dependability are caused by scaling trends in MOSFETs, operating constraints, process damage, and radiation damage. At the Si-SiO2 interface of the MOSFET, all of these degradation mechanisms lead to the formation of interface traps and localized charges. For instance, hot-carrier-induced deterioration in the form of interface traps in nanoscale MOSFETs caused by impact ionization in the channel near the drain junction has become a significant reliability issue since it reduces the design margin for circuits. Even a minuscule amount of interface traps/charges might negatively impact the device's performance due to the rising integration density of integrated circuits and the reduction in device size. Understanding MOSFET-level degradation, developing analytical models that include the effects of interface charges, and investigating new device architectures and techniques that are self sufficient in preventing the formation of interface traps are crucial for improving overall design efficiency. Newly designed device structure, like multi-gate architecture, helps reduce leakage currents, interface trap charges, and other detrimental short-channel effects. For instance, the Gate All xix Around (GAA) structure is considered to be one of the best multiple gate structures as it shows better gate controllability, suppressed floating body effect, and excellent CMOS compatibility, even at the nanoscale regime. Also, in short-channel devices, the fabrication complexity due to a steep source/drain and channel junctions is difficult. Other impacts like short channel effects and hot carriers are undesirably increasing when device design goes near and below the 20nm technology node. As a result of these factors, the junctionless transistor has been developed as a superior replacement for the junction-based transistor in addition to its remarkable properties. Since the source, channel, and drain regions are all uniformly strongly doped, no junctions can form, resolving the problem of impurity diffusion. With this in mind, a novel Junctionless Surrounding metal Gate Stack Nanowire FET Sensor device was designed to incorporate multi gate MOSFETs' advantages for high-sensing applications. This thesis investigates the sensitivity of junctionless gate stack Gate All Around NWFET devices and how they behave when subjected to hot carrier-induced interface localized charges. For instance, impact of localized charge on device electrical characteristics, such as IOFF switching ratio, drain currents, transconductance (gm), output conductance (gd), surface potential, intrinsic voltage gain, output resistance, device efficiency, and device sensitivity (shifting threshold voltage and subthreshold current ratio) have been examined. A 2D analytic model was also developed for surface potential, drain current and threshold voltage using the superposition theorem by applying the boundary conditions and validating at different silicon film radius channel lengths. The analytical model has been validated at different channel lengths and silicon film radii. The effect of varying gate work functions (gate optimization technique) on the performance of the device sensitivity was also studied. In addition to localized charge, the gate leakages seriously hamper the device performance at shorter channel lengths and impact the device sensitivity or performance; Due to this, a novel device architecture, “cylindrical Metal Gate (CMG) Dielectric Engineered (DE) JLNWFET,” was developed to improve device efficiency and sensitivity. In this direction, high Channel uniformly doping single/ dual/triple hybrid gate material engineering GAA NWFETsensors were designed to enhance their current driving capability and transconductance without increasing the electric field at the drain side. When MOS devices are utilized in sensing applications, the dielectric, which determines the performance and reliability of the device, also plays a crucial role. In this work, gate stack metal gate electrode GAA JL NWFET for various sensing applications has been investigated. Gate stack GAA JL NWFET with catalytic metal gate is studied for its use as a hydrogen gas sensor. Gate stack GAA JL NWFET with a nanocavity region for dielectric has xx been investigated for dielectric modulation-based biosensor applications. Also, an analytical model for gate stack GAA JL NWFETs with varied gate electrode engineering is established to study the impact of different gate electrodes on the performance of Gate stack GAA JL NWFET devices; analytical results are verified with device simulation results. Gate stack GAA JL NWFET shows much higher sensitivity for biosensing and hydrogen gas sensing in the subthreshold region as compared to conventional bulk MOSFET. The junctionless gate stack GAA NWFET' is a promising device architecture for creating a low-power, extremely sensitive, and nanoscale CMOS-compatible biosensor and hydrogen gas sensor due to its high surface-to volume ratio, low leakage current, and almost optimal subthreshold slope (SS) close to (60 mV/decade).