DESIGN AND COMPARISION OF DIFFERENT DOMINO TECHNIQUES

Abstract

Domino Logic gates are getting into the trend in designing the high-speed microprocessor due to their several advantages over static CMOS logic gates. The primary benefit of dynamic circuits incorporates speed and small chip region. But dynamic circuits also have several disadvantages such as huge leakage power dissipation and poor noise immunity. Power dissipation boosts drastically in high fan-in logic gates due to a rise in parasitic capacitance at the dynamic node. Owing to which the charging-discharging component of power dissipation amplifies, along with this noise margin of the logic gate also degrades. Many academics have put forward several compositions of domino circuits in order to tackle the problem of noise immunity and power dissipation. In this work, different domino techniques have been studied and a new composition of domino circuit has been proposed. In the proposed design both evaluation and keeper circuitries have been modified to minimize power dissipation and improve noise immunity respectively without affecting delay. Basically, in keeper setup, two keeper transistors in series have been utilized instead of one as in standard domino logic circuit. While in evaluation setup a transistor in diode configuration has been utilized along with a mirror transistor and an evaluation transistor. All the circuits have been simulated on a cadence virtuoso platform in a 180nm technology node. Three performance parameters that are average power dissipation, unity noise gain (UNG), and the number of transistors used are calculated to justify the efficiency of the proposed domino design. Results show that the proposed domino circuit gives around 81.1% reduction in power dissipation and 56% improvement in noise immunity than conventional domino without footer transistor circuit.