ENERGY EFFICIENT VOLTAGE LEVEL SHIFTER DESIGN IN NTV REGIME

Abstract

The constant demand for power efficient electronic systems has led to the exploration of low-power design techniques in various aspects of integrated circuits. In particular, voltage level shifters play a crucial role in bridging voltage domains within a system. This thesis focuses on the design and optimization of energy-efficient voltage level shifters operating in the Near-Threshold Voltage (NTV) regime. This work presents a low power and high-speed voltage level shifter circuit which can convert near threshold voltages to super threshold region. The proposed structure improves performance and speed by implementing a low power buffer to minimize power losses in the previous designs. High delay owing to fall transition has been mitigated using a pass transistor, which improves the overall speed of operation of the circuit without using any multi-threshold devices. Only 11 transistors are used for the proposed circuit. The circuit can shift input voltages as low as 0.3 V to 1V output voltage. The proposed LS was implemented using 45nm CMOS technology and incurs power dissipation of 12.78nW with propagation delay of 4.106 ns for a 0.4V/ 1 MHz signal. The designed circuit shows high speed performance as compared to other circuits present in the literature over a wide range of temperature.