DESIGNING OF RISC V ARCHITECTURE

Abstract

The University of California, Berkeley created instruction set architecture known as RISC V. Because the majority of CPU instructions were not used by most computer programmes, the RISC architecture was developed. The RISC V processor was introduced to reduce instruction set increase registers resource investment. Due to itstotal open source and free nature, this technology caught the attention of numerous IT conglomerates and start-ups. The word "RISC" refers to the "reduced instruction set computer” in the RISC V Processor. which only executes a small number of computer instructions, and "V" refers to the fifth generation. It is an ISA (instruction set architecture) for hardware that is open- source and is based on the well-established RISC idea. We designed processor that supports instructions each of 32 bit that propagate via five stages of pipelined registers for fetch, decoding, execution, memory access, and writeback. We have also demonstrated how instruction and data memory interconnected with the CPU core forming a whole processor. Pipeline facilitates simultaneous execution of many instructions and displays the working of an instruction within processor using data from the source and destination registers. Further, overcoming data hazard issue while executing instruction as upcoming instructions need updated value of register from previous one’s destination register through stalling by giving an extra cycle to wait and Forwarding unit where we can pass the data directly to next instructions in sequence without taking pause for a cycle to fasten the process and get correct values. Additionally, we used the Fibonacci program to evaluate the functioning of our processor and confirmed it by successfully having this series into memory. As a result, Various manufacturing firms have announced also offered RISC-V with open-source operating systems. This is a brand-new architecture that is offered under open, liberal, and cost-free licences. The chip and device manufacturing industries provided this CPU with marked support. Therefore, primarily made to be flexibly expandable and configurable for variety of applications. Professor David Patterson at the University of California, Berkeley created the RISC sometime in the 1980s. In two volumes titled "Computer Organization and Design" and "Computer Architecture at Stanford University," professors John Hennessy and David contributed their work. As a result, theywere giventhe ACM A.M. Turing Prize in2017.