FPGA IMPLEMENTATION OF OPTIMIZED AES ALGORITHM FOR MULTIMEDIA MESSAGES

Abstract

Ensuring secure communication of multi-media messages is crucial for social networking and data sharing platforms. Prevention of data manipulation and theft has led to the development of various encryption techniques, but scope remains for a fast and efficient multi-media encryptor. Advanced Encryption Standard (AES) is mathematically one of the most complex cipher algorithms to crack and has been widely deployed in the banking sector. The algorithm's mathematical framework and the implementation of numerous iterations of encryption procedures augment its security. AES has undergone exhaustive examination and scrutiny by the cryptographic community, unveiling no significant vulnerabilities. AES implementation for battery operated devices requires an algorithm with low power consumption and high-speed encryption/decryption of digital data. This dissertation proposes an FPGA implementation of a high throughput parallel pipelined 128-bit AES algorithm with a low power key expansion mechanism for iterative stages. A 128-bit symmetric key has been used for undertaking 10 rounds of transformations. All the encryption and decryption transformations are simulated using iterative design methodology in order to minimize hardware consumption. Xilinx Artix-7 FPGA device is used for hardware evaluation and Verilog HDL for programming. Simulation and synthesis task has been performed on Xilinx Vivado v2021.1 IDE.

The results exhibit high-rate encryption of 68 Gb/s and low energy consumption of 7 pJ/bit. Detailed study of the synthesized design has been undertaken to highlight the power consumption and performance of the algorithm at various operating voltages and temperature levels. The results have further been compared with existing work to substantiates its unwavering dependability and formidable efficacy. AES is integrated into a multitude of applications and systems, encompassing secure communication protocols, virtual private networks (VPNs), disk encryption software, and various other domains. A high throughput implementation of 256-bit AES cipher has also been carried out for encrypting digital images and explore its practicality in peer-to-peer communication. Pre-processing of images has been performed to make them suitable for encryption. A detailed study of the encryption results and histogram analysis has been carried out. The proposed algorithm achieved a Peak Signal to Noise Ratio (PSNR) of 61 dB for the decrypted image. Correlation between the input and the decrypted image was found to be 0.994 while the Mean Square Error (MSE) was calculated to be 0.0030. AES-256 has gained wide acceptance and standardization, making it compatible across different platforms, domains, operating systems, and devices. This compatibility facilitates interoperability and seamless integration into multimedia systems including video streaming, image protection, digital rights management, and secure multimedia communication.