AXI BASED IP BLOCK VERIFICATION USING UVM A DISSERTATION REPORT

Abstract

In modern VLSI, a DUT may have multiple interfaces. Each of these interfaces may have different UVM objects associated with them. In an SoC there are no. of IP blocks which are connected to each other with the help of interfaces. One such interface which is most commonly used is AXI interface. This project involves the verification of an AXI interface module that acts as an initiator or target depending on the upstream or downstream transaction. The module converts commands from the FIFO BFM or AXI BFM to AXI transactions or FIFO transactions. The testbench development is based on System Verilog using UVM methodology to create a constrained random test environment for faster verification. The testbench includes bus functional models of AXI and FIFO interfaces, which act as initiators/targets on the DUT's interfaces. The AXI interface is a widely used interface in digital designs and is popularly used for interconnecting different IPs within a SoC or FPGA. The AXI interface is complex, and verification of designs with AXI interfaces is challenging. The primary goal of this project is to verify the AXI interface module, which acts as an initiator or target depending on the upstream or downstream transaction. The AXI interface module converts the commands from the FIFO BFM or AXI BFM to AXI transactions or FIFO transactions. The verification is done using the UVM methodology, which creates a constrained random test environment, which helps in faster verification. The testbench includes bus functional models of AXI and FIFO interfaces, which act as initiators/targets on the DUT's interfaces. The AXI interface is a high-performance, high-frequency, and low-latency interface used in digital designs. The AXI interface provides the features of burst transfers, read and write data transfers, and different transfer sizes, including 8-bit, 16-bit, 32-bit, and 64-bit transfers. The AXI interface v also provides various features like data caching, out-of-order execution, and multiple outstanding transactions. The AXI interface module that is being verified in this project acts as an initiator or target depending on the upstream or downstream transaction. The module converts the commands from the FIFO BFM or AXI BFM to AXI transactions or FIFO transactions. The module is complex, and verifying its functionality requires a robust testbench. The UVM methodology is widely used for the verification of digital designs. The UVM methodology provides a standardized way of developing testbenches and allows for the creation of a constrained random test environment. The UVM methodology is based on the Object Oriented Programming(OOPs) concept, and it includes classes, objects, and virtual sequences. The testbench is an integral part of the verification process. The testbench includes the bus functional models of AXI and FIFO interfaces, which act as initiators/targets on the DUT's interfaces. The testbench verifies the functionality of the AXI interface module by generating random transactions and comparing the results with the expected output. The testbench also includes assertions and coverage to check the correctness and completeness of the verification process. In this project verification of AXI interface using IP system interface has done. In this entire designtwo units are there i.e initiator and target for upstream and downstream transactions.