STUDY OF LEAKAGE POWER REDUCTION TECHNIQUES IN CMOS CIRCUITS

Abstract

Now a days power dissipation has become major issues in CMOS VLSI circuits due to limited life span of the battery. The leakage power dissipation is one of the prime concern at lower technology nodes. It is a difficult and challenging task to design a CMOS circuit without any leakage issue. Also at lower technology nodes, the leakage current increases. So, there is a need to study techniques which reduces leakage current. In this study, the leakage power reduction techniques in CMOS circuits namely ONOFIC, stack ONOFIC, LECTOR and LCPMOS have been investigated. Here the basic logic gates namely NAND, NOR and sequential circuits like D flip flop and Up counters also have been examined. It is found that these techniques offer higher resistance to the path when in OFF state due to which it reduce the leakage current when compare to conventional circuits. In this work for simulation LT Spice tool has been used and all the circuits are examined using 32nm technology node. Using ONOFIC technique on an average 79.57% leakage power have been reduced in static circuits and 95.69% leakage power have been reduced in sequential circuits. Using stack ONOFIC technique on an average 34.02% leakage power have been reduced in static circuits and 94.51% leakage power have been reduced in sequential circuits. Using LECTOR technique on an average 98.47% leakage power have been reduced in static circuits and 98.34% leakage power have been reduced in sequentialcircuits. Using LCPMOS technique on an average 85.364% leakage power have been reduced in static circuits.