DESIGN AND IMPLEMENTATION OF EFFICIENT MATRIX MULTIPLICATION USING VARIOUS ARCHITECTURE

Abstract

The semiconductor industry plays a crucial role in the design and manufacture of integrated circuits (ICs) used in a wide range of electronic devices. VLSI technology allows for the integration of millions of transistors onto a single chip, enabling the creation of highly complex and powerful devices such as computers, smart phones, and other electronic devices. The VLSI industry is a key driver of innovation in the electronics industry and has played a major role in the development of new technologies and the proliferation of electronic devices in our daily lives. Consequently, area, speed, and power play a critical role in any circuit design .A circuit must be created to meet the present trend's requirements with minimal space and minimal time limitations. Matrix multiplication is of significant importance in various fields and applications. Matrix multiplication plays a fundamental role in linear algebra, solving system of linear equations, data analysis and machine learning, computer graphics and computer vision, network theory and graph algorithm, etc. This thesis gives a thorough investigation into how the Wallace tree multiplier, Vedic multiplier, and parallel prefix adders might be combined to enhance matrix multiplication performance. These techniques contribute to achieving significant speed improvements, reduced and optimized resource utilization. The findings of this study add to understanding of digital circuit design by offering suggestions for choosing and incorporating effective multiplication methods for matrix operations. The thesis provides helpful advice to researchers and designers of digital circuits by explaining the trade-offs, benefits, and drawbacks of the integrated architecture. Firstly, Ripple Carry adders, Kogge Stone adders, and Han Carlson adders have been designed and analyzed. After that, the Wallace tree multiplier and Vedic multiplier are designed using these adders. By combining both multiplier and adder, matrix multiplication designs, analyses the performance data, and interprets the results obtained from the experiments. Using the ISE Design Suite tools in Verilog, all circuits are created and simulations are run. The XC6SLX150T are the devices used for synthesis.