A COMPARATIVE ANALYSIS AND DESIGN OF DYNAMIC LATCHED COMPARATORS

Abstract

In an attempt to study various comparators, a comparative analysis of different dynamic latch comparators have been performed. The performance of the conventional dynamic latch comparator, Double tail dynamic latch comparator, charge sharing dynamic comparator and modified double tail dynamic latch comparator have been done to display the improvements achieved. Further a new circuit has been proposed displaying the same functionality. Transient analysis has been observed for each circuit. Effect of delay on circuit’s robustness in form of Monte Carlo Simulations has been performed. As the need for low power, high speed comparator’s is of utmost importance day by day, the circuits present a vivid picture of their performance. All the simulations are carried out using Cadence Virtuoso tool with a supply voltage of 1.5V, differential input voltage of 20mv and common mode voltage of 1.2V in 130 nm CMOS technology node at a temperature of 27-degree Celsius.