FORMAL TECHNIQUES TO VERIFY FUNCTIONALITY OF DIGITAL MEMORY DECODER

Abstract

This report discusses the formal property verification of physical digital memory decoders, which are a crucial component of most digital integrated circuits. We present a formal verification technique that is suitable for verifying the correctness of physical layer digital memory decoders. The method is based on a formal language for describing the system, which is then verified using Formal Property Verification techniques. To handle the complexity of the model, we also introduce a novel abstraction technique that reduces the number of states in the model while preserving its behavior. This abstraction technique enables more efficient verification of the model, reducing the time and computational resources needed to verify its correctness. We discuss the results of the verification process and compare the results with those obtained using traditional simulation techniques.