STUDY AND DESIGN OF LOW POWER TECHNIQUES FOR CMOS CIRCUITS

Abstract

This thesis addresses a significant challenge faced by the VLSI industry today, namely low power designs. The pursuit of low power design has been a driving force for the industry for a considerable period. However, the emergence of high-performance portable battery operated devices has introduced a new dimension to the design perspective of designers. While CMOS design has been widely adopted due to its robustness and low static power consumption, the increase in transistor density and the reduction of transistor size below the sub-micron level have compromised CMOS's low power characteristics. Consequently, there is a critical need for enhancing CMOS circuits for low power applications. This thesis investigates two approaches for reducing leakage in CMOS designs. The first approach involves a hardware-based solution, where a 4×4 multiplier is designed incorporating leakage reduction techniques such as stacking, ON/OFF IC, LECTOR, and MTCMOS. By comparing the effectiveness and efficiency of these techniques in reducing leakage power, the most suitable approach within the hardware domain can be identified. The second approach focuses on a software-based solution known as Input Vector Control (IVC). IVC capitalizes on the varying levels of activity exhibited by different input patterns, resulting in different levels of leakage power consumption. This thesis proposes a novel Python-based input vector control algorithm that enhances the accuracy and efficiency of the IVC technique in real-world scenarios. As a future direction, these two approaches can be combined for even better results.