VEDIC MATHEMATICS-DRIVEN APPROACH TO HIGH-SPEED AND ENERGY-EFFICIENT ALU DESIGN

Abstract

This dissertation presents a Vedic Mathematics-driven approach to designing high-speed and energy-efficient Arithmetic Logic Units (ALUs) using Xilinx Vivado. ALUs are essential components in digital systems, and the demand for improved performance and reduced power consumption continues to grow. Traditional ALU designs often suffer from complex architectures and high power consumption, limiting their efficiency. The proposed approach leverages the principles of Vedic Mathematics, an ancient Indian system known for its simplicity and efficiency. By applying Vedic Mathematics techniques, the design methodology aims to achieve high-speed computation and reduced power consumption. Complex arithmetic operations are decomposed into simpler computations using Vedic Mathematics sutras (aphorisms), which provide efficient algorithms for addition, subtraction, multiplication, and division—core functions of an ALU. Additionally, the Vedic Mathematics-driven ALU design incorporates optimization techniques, such as clock gating, to further reduce power consumption. Clock gating selectively disables the clock signal to inactive circuit blocks, reducing unnecessary power consumption. By strategically organizing and optimizing arithmetic operations based on Vedic Mathematics principles and implementing clock gating, the proposed design achieves improved energy efficiency while maintaining high-speed performance. The effectiveness of the approach is demonstrated through comparisons with traditional ALU designs in terms of speed and power consumption. The project was implemented using Xilinx Vivado 2020.2, and Artrix-7 FPGA for synthesis. Experimental results show notable improvements in both speed and energy efficiency compared to traditional designs, validating the effectiveness of the Vedic Mathematics-driven approach combined with clock gating.