POST SILICON FUNCTIONAL VALIDATION : PCLE

Abstract

Post Si validation is one of the most important and crucial step in the PRQ of the product into the market. As, in this era, there are a lot of IPs or peripherals are present on the SoC and also contains complex circuitry on in the chip. Major chunk of the silicon chip constitutes analog and digital circuits which contains high speed input output link interface called PCIe and other parallel links for example DDR. Validation of this link interface IPs are very hard to validate as the observability of the signals are very less in the post Si domain. This thesis proposes functional validation of high speed serial links such as PCIe to improve the quality and Performance of the IP in the SoC with the help of correct debug tools. And, also describes the systematic approach to validate the IP in a correct way and to meet the market timing constraints