DESIGN AND ANALYSIS OF A LOW POWER AND HIGH PERFORMANCE 10T SRAM CELL AT 32 NM TECHNOLOGY NODE

Abstract

Memory is known to be one of the most crucial parts of any electronic system. However, a class of memory called the cache memory is even more crucial among the type of memories since it is the one working closely in synchronization with the central processing unit. There are millions of SRAM cells inside cache memory. SRAM cells must therefore possess a few essential attributes for cache memory to be reliable, including low dynamic and static power consumption, high data stability, and low read latency. A comprehensive review of the design and analysis of SRAM cells are performed, focusing on the fundamental building block, the SRAM cell, and its critical performance parameters. The aim is to provide a concise overview of the key concepts and challenges involved in SRAM cell design, highlighting recent advancements and future directions. The review begins with an introduction to SRAM and its significance in various applications. It explores the basic structure and operation of an SRAM cell, emphasizing the importance of stability, read and write capabilities, and power consumption. The different SRAM cell topologies are discussed, along with their advantages and trade-offs. The critical design considerations of SRAM cells, including noise immunity, process variations, and leakage current. Various techniques for improving the stability of SRAM cells, such as the use of feedback and assist circuits, are examined. Moreover, the impact of scaling technologies, such as process technology nodes and transistor scaling, on SRAM cell performance is explored. Additionally, the analysis of SRAM cell performance metrics, including read and write access times, write margin, stability, and power dissipation have been studied. The influence of key parameters, such as supply voltage, transistor sizing, and load capacitance, on these metrics is discussed. Furthermore, the impact of process variations on yield and reliability is addressed, along with reliability-enhancement techniques. To successfully incorporate these qualities, a comparative analysis of different 10T and 11T SRAM cells has been performed. The performance of the conventional TG10T and 11T SRAM models are compared to the 10T SRAM to showcase enhancements obtained. TG10T SRAM cell deploys two transmission gates instead of two NMOS access vi transistors to strengthen writing ability. It also employs two additional buffer transistors so that read stability can be enhanced. The TG10T SRAM cell is proven to be more enhanced in almost every aspect but it consumes more power. The read SNM and write SNM are found to be the largest in the TG10T SRAM cell. The power dissipated by the TG10T cell (i.e., 233.69nW) is approximately two times as compared to the 10T SRAM cell (i.e., 108.65nW) and 11T SRAM cell (i.e., 88.491nW). The analysis also shows that both read and write delay is minimal in TG10T SRAM cells. The read delay is 343.3 psec and the write delay is 494 psec respectively. A 10T SRAM cell has been proposed and comparison between of different existing 10T and 11T SRAM cells has been performed. The power consumption and read-write behaviors of all the SRAM cells are studied. The power consumed by the TG10T cell (i.e., 233.69nW) is approximately two times in contrast to the 10T SRAM cell (i.e., 108.65nW) and five times when collated to the proposed 10T SRAM cell (i.e., 44.794nW). The analysis associated depicts that the read and write delay is minimum in the proposed 10T SRAM (i.e., 97.7psec & 154.3psec) respectively. All simulations are carried out using LTSPICE software operating at 0.5 Volt in 32 nm CMOS process technology. The proposed transmission gate based 10T SRAM cell consumes minimum power and has better overall read stability as compared to the other designs. The review concludes by highlighting emerging trends and challenges in SRAM cell design, including the exploration of novel device architectures, non-volatile SRAM, and low power designs for energy-efficient computing systems. It emphasizes the need for continued research and innovation to address the increasing demands for higher density, lower power consumption, and improved reliability in future SRAM cell designs. A comprehensive overview of the design and analysis of SRAM cells serves as a valuable resource for researchers, engineers, and students working in the field of digital integrated circuit design, offering insights into the current state of SRAM cell technology and potential future directions.