PERFORMANCE ANALYSIS OF AN IMPROVED 8T SRAM CELL FOR LOW POWER AND HIGH SPEED APPLICATIONS

Abstract

Memory is already known to be one of the most crucial parts of any electronic system. However, a class of memory called the cache memory is even more crucial amongst the type of memories since it is the one working closely in synchronization with the central processing unit (CPU). It is a faster and smaller memory and is also used to store data frequently used by the CPU. Its usage is inevitable in any system that performs computing digitally in any way. Cache memories consist of large arrays comprising millions of SRAM cells, which serve as the fundamental components of the cache memory system. As the ceiling of advancement of technology becomes higher, so does the demand of enhanced cache memories and hence the SRAM cells. Enhancement of these cells may be in the form of different parameters, but the crucial parameters that this paper will be focusing on are noise margins, access delay, power consumption, sturdiness to temperature and voltage drop variation, etc. Keeping the mentioned parameters as the guiding principle, a single ended, dual port SRAM cell architecture consisting of 8 transistors is proposed in this thesis work. The memory cell under discussion incorporates several key design features to optimize its functionality. Firstly, it utilizes separate bitlines for read and write operations, ensuring independent and isolated functioning of these operations without any conflicts. Secondly, the storage node, formed by back-to-back inverters, remains undisturbed during read operations, resulting in enhanced data stability and reliability. Moreover, the cell employs dual VT (threshold voltage) transistors to minimize leakage power consumption, thereby improving energy efficiency. Lastly, the configuration of transistors within the cell is optimized to minimize the number of transistors in the read critical delay path, leading to reduced read delays and improved overall performance. These design considerations collectively contribute to the cell's efficiency, reliability, and speed, making it a valuable component for memory systems. However, upon closer inspection, this model suffers from a concerning shortcoming, that is, its write performance is very unsymmetrical, and lower than most of its counterparts. Thus, to make an improvement in this aspect and other aspects very crucial to SRAM functioning, another SRAM cell consisting of 8 transistors is proposed in this thesis work. vi The performance indicating parameters of the suggested cell is also compared alongside five other models using the same technology node, supply voltage and identical simulation conditions. After conducting transient analysis on the proposed SRAM cell, the results indicate a read delay of 83 picoseconds (pS) and a write delay of 126 pS. Analysis of power consumption shows that the proposed SRAM cell consumes dynamic read and write power of 12.8 µW and 10.4 nW respectively and a static power consumption of 0.932 µW. It was also observed to have static read noise margin of 140.8 mV and hold noise margin of 143.5 mV each and a write margin of 400.6 mV. Supply voltage variation to emulate voltage drop variation reveals variation of hold, read and write margin as shown in the graphical representations below. Further, temperature variations were simulated which showed that hold margin varied at 0.77 mV/℃, read margin at 0.79 mV/℃ and write noise margins at 0.58 mV/℃.