DESIGN OF A NOVEL TERNARY D FLIP-FLOP BASED ON GNRFET

Abstract

For decades, computing logic uses Binary circuits based on Complementary metal oxide semiconductor (CMOS) technology. However, as the trajectory of Moore's law is ascending, classical Binary logic and CMOS technology fail to cope with the VLSI industry's advancements. Multiple-Valued Logic (MVL), along with Graphene Nano Ribbon Field Effect Transistor (GNRFET) technology, have the potential to become the successor of classical CMOS technology. MVL, with its high information density and GNRFET's many characteristics, like its high Ion-Ioff ratio, low propagation delay, and adjustable threshold voltage, makes them an ideal combination to take over current technology. Latches and Flip-Flops are the essential parts of any digital computational applications for real-time data processing systems. Hence designers try to make an efficient Flip-Flop design based on the trade-off between the design constraints like speed, power, and area. In this project, two new designs of Ternary D Flip-Flop (TDFF) are proposed and compared with their predecessors based on Power Consumption, Propagation Delay & Transistor Count. All the circuits are simulated & analysed in HSPICE using the GNRFET model present on the Nanohub website.