COMPARISION OF POWER AND PERFORMANCE OF FULL-ADDER USING DYNAMIC CMOS LOGIC, NORA LOGIC, AND NORA LOGIC WITH MTCMOS OF SUB-45nm TECHNOLOGY NODE

Abstract

In digital systems, arithmetic operations play a major role and full adder is the center of focus of all arithmetic operations. By using static CMOS logic, transmission gates, dynamic logic, or pass transistor logic we can design a full adder. Here, the main focus is on Dynamic Logic because of its high performance and low power consumption. We have also proposed a hybrid of MTCMOS logic and NORA logic by introducing high-Vt transistors near the supply and ground to minimize leakage power because leakage is very high in Deep Submicron technology. We have also done a comparison of dissipated power and propagation delay of full-adder based on Basic Dynamic CMOS logic, NORA Dynamic Logic, and MTCMOS with NORA Dynamic Logic of 45nm, 32nm, 22nm high k dielectric Predictive Technology Model (PTM) has been implemented for a constant supply.