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http://dspace.dtu.ac.in:8080/jspui/handle/repository/19709| Title: | DESIGN OF SERDES & DESIGN OF MULTICORE PROCESSOR FOR MATRIX MULTIPLICATION |
| Authors: | SINGH, SIDDHARTH |
| Keywords: | DESIGN OF SERDES MULTICORE PROCESSOR MATRIX MULTIPLICATION |
| Issue Date: | Jun-2022 |
| Series/Report no.: | TD-6235; |
| Abstract: | This project covers the analysis, design and simulation of two different work done by me for project which was the design of SerDes system and multiprocessor working. SerDes is a pair of blocks that is used in high-speed communication and to compensate for limited input/output. Conversion of serial data in parallel interfaces takes place in these blocks. For this project I have simulated the serializer part of the SerDes. Multicore Processor is designed to have matix multiplication in which every core has its own ALU,control unit and registers. |
| URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/19709 |
| Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Siddharth M.Tech.pdf | 5.19 MB | Adobe PDF | View/Open |
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