DESIGN OF SERDES &  DESIGN OF MULTICORE PROCESSOR FOR MATRIX  MULTIPLICATION

DSpace JSPUI

Learn More

Please use this identifier to cite or link to this item: http://dspace.dtu.ac.in:8080/jspui/handle/repository/19709

Full metadata record

DC Field	Value	Language
dc.contributor.author	SINGH, SIDDHARTH	-
dc.date.accessioned	2023-05-25T06:12:16Z	-
dc.date.available	2023-05-25T06:12:16Z	-
dc.date.issued	2022-06	-
dc.identifier.uri	http://dspace.dtu.ac.in:8080/jspui/handle/repository/19709	-
dc.description.abstract	This project covers the analysis, design and simulation of two different work done by me for project which was the design of SerDes system and multiprocessor working. SerDes is a pair of blocks that is used in high-speed communication and to compensate for limited input/output. Conversion of serial data in parallel interfaces takes place in these blocks. For this project I have simulated the serializer part of the SerDes. Multicore Processor is designed to have matix multiplication in which every core has its own ALU,control unit and registers.	en_US
dc.language.iso	en	en_US
dc.relation.ispartofseries	TD-6235;	-
dc.subject	DESIGN OF SERDES	en_US
dc.subject	MULTICORE PROCESSOR	en_US
dc.subject	MATRIX MULTIPLICATION	en_US
dc.title	DESIGN OF SERDES & DESIGN OF MULTICORE PROCESSOR FOR MATRIX MULTIPLICATION	en_US
dc.type	Thesis	en_US
Appears in Collections:	M.E./M.Tech. Electronics & Communication Engineering

Files in This Item:

File	Description	Size	Format
Siddharth M.Tech.pdf		5.19 MB	Adobe PDF	View/Open