ANALYSIS AND DESIGN OF POSITIVE FEEDBACK SOURCE COUPLED LOGIC

Abstract

The demand for consumer electronics, biomedical implantable systems, sensor nodes in sensor networks etc. have all contributed towards the drive for portable systems with long battery life. This in turn has driven the need for mixed signal integrated circuits with analog and digital logic on the same substrate as this reduces dimensions of the integrated circuits, reduces the cost and also allows operation at higher speed. However, the noise transmission from the digital part to the analog part which is sensitive to noise becomes a problem, because of the loss in accuracy of the analog circuits or the reduction of the dynamic range. In CMOS circuits, the noise is due to current peaks and voltage variations during the switching of logic states. To solve this, several solutions are proposed – in terms of layout, placement of pins and routing of signals and selection of alternate logic styles. To address the switching noise, various low switching noise logic styles have emerged wherein power supply current is kept nearly constant during the switching event and/or working with smaller voltage swings. Some notable logic styles are current steering logic (CSL) style, current balance logic (CBL) style, folded source-coupled logic (FSCL) style and the source coupled logic (SCL) style. The positive feedback source coupled logic (PFSCL) style, a variant of SCL, among these is an attractive alternative as it addresses the issue and is explored in this thesis for design modifications to improve the overall circuit performance. The work in this thesis encapsulates its analysis and design. The PFSCL FC based gates help in accommodating complex logic function into a single gate, but requires larger footprint. The concept of multithreshold technique is incorporated and two vii topologies are presented. The former results in area advantage while the latter improves power consumption. The static and dynamic parameters are modelled and validated. Next, a PFSCL Quadtail cell that can accommodate more inputs in a single gate is presented thereafter. The usefulness of the proposal is illustrated with a three input PFSCL XOR gate. The proposition is analysed for static and dynamic parameters. It is found that the proposed XOR gate topology outperforms the possible existing counterparts. The presence of a constant current source in PFSCL causes static power consumption which restricts its application for battery constrained devices. The availability of dynamic PFSCL style is an effort made in this direction. This style, however, requires cascading of gates for multilevel realisation and also intermittent buffers for correct evaluation. Two schemes are worked out to address this – the former modifies the pull down network of existing D-PFSCL gate while the latter relies in inclusion of transmission gates. The ultra-low power PFSCL gate is introduced in this work wherein low power supply is used and the constituent transistors operate in subthreshold region. The basic principles for design of PFSCL in subthreshold region are identified and trends are noted. From analysis and simulations it is noted that the circuits implemented using PFSCL style in subthreshold region offer more flexibility to the design of ultra-low power applications compared to those implemented using CMOS in subthreshold region. All the propositions are validated through extensive simulative investigations.