SIMULATION AND ANALYSIS OF Ⅲ-Ⅴ COMPOUND SEMICONDUCTING HETERO MATERIAL BASED JUNCTION-LESS TUNNEL FET FOR IMPROVED PERFORMANCE

Abstract

Tunnel FET has been proved to be the best alternative to the conventional MOSFET in low power electronic applications. In this thesis, various techniques have been proposed to enhance the performance of a TFET device by improving the key parameters like ON current (ION), threshold voltage (Vth), steeper subthreshold swing (SS), ambipolar conduction, and parasitic capacitances using Technology Computer Aided Design (TCAD). The initial focus is to reduce the fabrication complexity of doping junctions with a charge plasma based junctionless TFET architecture by consolidating the advantages of both a junctionless FET (higher ON current, ION) and a TFET (steeper subthreshold swing, SS). To elevate the ION and suppress the leakage current (IOFF), bandgap engineering has been implemented by utilizing the III-V compound semiconducting hetero-material (InAs/GaAs) source/channel (S/C) tunneling interface. Further, dual material gate (DMG) engineering has been applied by choosing a lower work function tunnel gate (TG) towards the source region and a higher work function supplementary gate (SG) towards the drain region. The 2-D TCAD simulations have been executed to explore the impact of TG process variations - work function and length on analog/RF and linearity figure of merits (FOMs) of DMG-HJLTFET. The extracted result parameters have also been compared to single metal gate (SMG)-HJLTFET and conventional Si-JLTFET. The work function and length of TG is optimized to attain the best device characteristics. A significant band bending has been established at the hetero material tunneling interface of DMG-HJLTFET leading to narrower barrier width by the application SAMRITI SHARMA vi of DMG engineering. The SS of DMG-HJLTFET is 52.4% and 88.8% reduced in comparison with SMG-HJLTFET and Si-JLTFET due to the energy-band profile modulation obtained by dual-material gate technology and Ⅲ‐Ⅴ compound semiconducting materials. The DMG-HJLTFET exhibits a high current switching ratio of 3.1 × 1011 as compared to SMG-HJLTFET (1.4 × 1011) and Si-JLTFET (1.8 × 106 ). The use of mono-dielectrics (low-k or high-k oxides) in the oxide region of H-JLTFET leads to poor ION due to the ambipolar conduction. Therefore, a heterogeneous gate dielectric (HD) engineering is executed by developing a heterogeneous gate dielectric stack having high-k and low-k material in the oxide region under control gate (CG) nearby the source and drain regions, respectively. The performance of HD-HJLTFET has been compared with mono-dielectric high-k HJLTFET and low-k HJLTFET. The selection of an appropriate high-k oxide for the hetero dielectric and length of the high-k oxide in HD-HJLTFET has been optimized using different dielectric materials - HfO2 (k = 25), ZrO2 (k = 22), Al2O3 (k = 9), Si3N4 (k = 7), and SiO2 (k = 3.9) in the high-k region. The superior performance of HD-HJLTFET in terms of ION, current switching ratio (ION/IOFF), device efficiency, and SS makes it an appropriate alternative for low power and fast switching applications. However, developing a hetero-structure TFET using an amalgamation of InAs (binary)-AlGaSb (ternary, in place of GaAs-binary) Ⅲ-Ⅴ compound semiconducting materials provides a tunable bandgap at the S/C interface of H-JLTFET, where the energy bandgap of ternary material, AlxGa1- xSb depends on the Al-mole fraction value (x.composition). The properties of AlxGa1-xSb can be modified by changing the x-composition, therefore the device structure can be optimized for best outcomes by using this material in the channel and drain region. The suitability of lattice matched standard Ⅲ-Ⅴ growth and processing techniques are the prime reason for choosing these materials. The superior performance is attributed to the conduction band local minima induced at the channel yielding to narrower tunneling barrier width at an optimized Al-mole fraction (0.15) of AlGaSb. 77 times higher gm of H-JLTFET led to 5×106 and 205 times higher device efficiency and fT along with SAMRITI SHARMA vii ~66% reduction in the parasitic capacitance making it favorable for high-speed switching applications as compared to Si JLTFET. The interface trap charges (ITCs) at the semiconductor/oxide interface originating during the fabrication process of electronic device plays an important role in reliability issues. In real environment, a higher number of positive and negative ITCs develop at the Si-SiO2 interface while fabricating the device. These ITCs strongly affect the reliability of the device. Therefore, the impact of ITCs polarity and density has been analyzed for HD-HJLTFET and has been compared with the ideal case of defect free device. The high-k dielectric towards S/C interface and low-k dielectric towards D/C interface in HD-HJLTFET results in enhanced analog/RF performance metrics with negligible variation against different ITC polarity than its counter device. The linearity parameters of HD-HJLTFET (VIP2, VIP3, IIP3, 1dB compression point, and IMD3) also showed marked improvement with negligible variation against different ITC polarity than its counter device, making it more reliable for low power microwave and distortion-free wireless communication systems. Till now only polar gate (PG) and CG are considered responsible for the retention of hole plasma and electron plasma in JLTFET. However, polar gate is not the only one responsible for the retention of hole plasma in the p+ prompted source but the hole plasma near the interface of source electrode metal and p+ prompted source (SEM/S) is influenced by the choice of source electrode metal work function too. Therefore, a comprehensive investigation of the mutual significance of PG and SEM work function on p+ prompted source has been done by considering three metals – W (4.55 eV), Mo (4.65 eV), and Pd (5.3 eV) as the source electrodes in HJLTFET. The Schottky tunneling phenomenon is considered by implementing the Universal Schottky Tunneling (UST) model to study the underestimated drain current of HJLTFET and the preference of ohmic contacts over Schottky contacts has also been discussed. However, the UST model becomes inconsequential for SEM work function higher than p+ prompted source (Pd) as hole plasma is preserved by the ohmic contact formation.