HIGH SPEED AND EFFICIENT DESIGN OF DETMB-FF WITH CLOCK GATING

Abstract

Two efficient low power design strategies are Data-Driven Clock-Gating (DDCG) and Multi-bit Flip-Flops (MBFF), in which various FF is grouped with one clock. Even if the VLSI designers are often used, they are typically handled individually. The previous study has focussed on the use of MBFF in RTL, gate-level, and layout. Conflicts and contradictions were created by studying all aspects of the common design as a whole and trying to wrap all of that up into one architecture of the internal circuit of MBFF, its multiplicity and its synergy with FFs data have not yet been studied. Maximizing the savings by developing a strategy combining DDCG and DET-MBFF. The DET-FFs should be grouped in MBFFs in increasing order of their activities to optimize the power area delay savings. The algorithm was used in a realistic design flow to create a power savings model based on DET-MBFF multiplicities and FF toggling probabilities. By using the Xilinx ISE unit, we were able to save power area delay compared to designs with ordinary FF.