SIMULATION AND EMULATION OF DIGITAL CIRCUITS AND MEMORY PORTS

Abstract

The Simulation and Emulation of the digital circuits are discussed in this present work in which there is an enhancement to increase the capacity and performance of the digital chips and ICs where it reduces its size with help of the memory inference in complex circuits, the number of multiplexers, adders and subtractors are replaced with the memory block which reduces the area of the digital ICs and the capacity of the digital circuit is getting enhanced. It also reduces the compilation time of the simulating circuits during gate level and behavioral level synthesis of the circuit. The importance of the work is that all the circuits and ICs can be tested in fraction of seconds using this optimization which reduces a lot of money and time consumption of an organization. The testing of this optimization is done by simulating the module where the analysis of the various scenarios is done on simulator. The optimization is further tested on emulator where the replica of the module can be created, the emulator can act as the same piece of hardware where the compilation time is reduced. Methodology adopted is Verilog and VHDL the hardware descriptive language is used. All the scripting of the various scenarios is done with shell scripting. The coding for the optimization of memory ports is written in C/C++ in which all the read and write ports are analyzed. In memory optimization enhancement various tools for simulation like Questa and precession are used for simulating all the modules of the hardware descriptive Language. Further, for creating the Real Replica of the hardware, emulator is used where the Register transfer level compiler and Emulator (Veloce) are used of validating all the results in velcomp flow where the quad core processor is used , all the modules are compiled in the parallel manner . It makes the system for informative in which core processor, it is compiling all the Modules with high speed and efficiency. So this optimization reduces the speed of the simulator and emulators in terms of the area and the compilation time of the gate level synthesis where the register transfer level design is transformed into logic gates.