SRAM DESIGNS FOR NANOMETER TECHNOLOGIES

Abstract

High performance applications, such as biomedical and wireless sensor networks, require low power circuits for extended time operation. Supply voltage scaling in such systems is an effective way to lower the power consumption. Although voltage scaling has benefits, it has brought serious challenges for designing reliable digital circuits including Static Random Access Memories (SRAMs). Further, as SRAM occupies a significant area on SoC, the memory failures may lead to complete collapse of the system. The conventional 6T SRAM cell has been the industry standard for a long time. However, it has limitation in operating reliably at lower voltages due to reduced margins and other performance related issues. Therefore, conventional 8T SRAM cell with improved margins has emerged as the potential substitute for its 6T counterpart. In nanometer regime, the leakages and PVT-variations become significant culminating into degraded performance and restricting its usage in sub-threshold region in small-geometry devices. As sub-threshold leakage dominates the total leakages in SRAM cell in nanoscale devices, the classification of sub-threshold leakage reduction techniques and their impact on performance parameters under various operating conditions need extensive analysis. The available techniques are classified as those addressing leakage current component at the level of latch, bitline and read port levels; and their impact on major performance parameters is evaluated. Since the performance of a technique is also susceptible to PVT variations, this aspect is also considered for suggesting the best suitable operating conditions for a technique falling under each classification. A low leakage SRAM cell based on the use of leakage reduction techniques is also presented. The latch and bitline leakages are respectively addressed through Multi threshold CMOS and Negative vii wordline techniques in the cell. Further, Multi threshold CMOS technique is applied to non-critical transistors in the latch core to avoid its degrading effect. There are issues in read and write operation of nanometer SRAMs and isolated read port is popular technique used to address this. The trade-off existing between the read current and read bitline leakages needs examination. To address this issue, two new SRAM cells with an isolated read port are proposed in this work. In the first proposed cell, the write performance is improved by incorporating write assist transistor with single ended write to reduce power consumption. An attempt is made to achieve high read current values by removing the stacking of MOS transistors in the read port. The second proposed cell addresses yet another issue of nanometer SRAM cells i.e. read bitline leakages. It uses compensation transistor which suppresses and equalizes read bitline leakages in un accessed cells irrespective of the stored data resulting in low and data-independent leakages in SRAM cell. Additionally, it provides the reverse current in accessed cell to maintain high read bitline voltage while compensating read bitline leakages in un accessed cell. The reduced stacking effect of transistors further helps in maintaining reasonable values of read current resulting in significant improvement in all the read performance parameters. For improvement in write mode, the proposed cell employs faster differential write. With reduced supply voltage and device scaling, the issue of PVT-variations has also emerged as a serious design challenge for nanometer SRAMs. This issue is addressed in the literature by incorporating Schmitt-trigger inverters for latch core in SRAM cells. However, a Schmitt-trigger based SRAM cell that can address the major performance parameters in all the three operating modes is not available in literature. In this regard, a new Schmitt-trigger based SRAM cell is presented that provides data-independent viii tolerance against PVT-variations in all the three modes. The proposed cell provides better write performance due to the presence of novel combination of Negative bitline write assist technique with modified Schmitt-trigger action. Further, fully-gated grounded scheme is used in isolated read port to reduce read bitline leakages. FinFET is emerging as an alternative to CMOS technology due to its good scaling ability, high ON current, reduced Vth variations, better sub-threshold slope and short-channel effect. Therefore, an attempt is made to propose a FinFET based SRAM cell with an isolated read port that can address the issues of existing cells such as reduced stability of stored data, increased bitline load capacitance, increased leakages etc. The proposed cell achieve better data stability due to the isolation of internal storage nodes from external bitlines. The read bitline leakages are also reduced in un-accessed cells by maintaining similar operating conditions in the read port, independent of stored data values. Further, the increased driving strength of FinFET based cell results in high read current values providing significant improvement in read performance parameters. Additionally, the use of write assist transistor helps in quick charging of internal storage nodes resulting in faster write operation. In the thesis, the performance of all the proposed SRAM cells is analyzed and compared based on various standard cell metrics. The functionality of proposed cells is verified in all the three operating modes and performance simulations are done using 32 nm bulk CMOS PTM model parameters. Further, the performance of FinFET based cell is verified using 22 nm FinFET PTM model parameters.