LOW POWER ACCURACY CONFIGURABLE MULTIPLIER USING NEW CARRY MASKABLE ADDER AND FS-GDI TECHNIQUE

Abstract

Adders and multipliers are important arithmetic modules in the efficacy and performance of digital signal processor (DSP) systems. The speed and power consumption of arithmetic units have an impact on processor efficiency. It is improved by using approximation computing in arithmetic units with tolerable output degradation. Approximate computing is a recent concept that aims to create a cost-effective design strategy while sacrificing computational quality for error-tolerant applications. Approximate computing can be used in research at both the hardware and software levels. In mathematical and logical procedures, adding is the most important step. Approximate Computing is used in VLSI design to reduce the number of transistors, delay, and power limitations. The employment of approximate adders in error-prone applications is viable since approximate addition is considered to be an effective energy trading technology in terms of performance and accuracy. Accuracy that can be customised Approximate Adder designs have been shown to be effective in alleviating these constraints. Using Full Swing-Modified Gate Diffusion Input (GDI) approach, a new circuit design for a Carry Maskable Adder has been presented. Proposed circuit design simulations have been simulated out in 45-nm process technology using LTSpice XVII. The results indicate 37% and 32% reduction in Power and Delay respectively. Using the proposed Adder a low power accuracy configurable Multiplier is designed and simulated out in 45nm process technology using LTSpice XVII. The results indicate 51.2% and 37% reduction in Power and Delay respectively.