DESIGN OF HIGH STATIC NOISE MARGIN TRANSMISSION GATE BASED SRAM CELL

Abstract

SRAM cell is the most commonly used embedded memory in System-On-Chip; it occupies the largest portion of the chip area and dominates the total chip power. Reducing the power consumption of the SRAM cell and enhancing the static noise margin is very important to improve system performance, efficiency and reliability. The conventional 6T SRAM cell suffers from the read destruction problem. In this report a new 10T SRAM cell design based on transmission gates is represented. The proposed design uses a separate read path, thus no voltage division between the storage node and the bitline, the read stability is maintained as equal as the hold stability. The conventional 6T SRAM cell has two bitlines for read and write operation, The proposed SRAM cell operates by charging / discharging of a single bit-line (BL) during read and write operations thus results in reduction of dynamic power consumption. The proposed design has been simulated at 32 nm technology node using LTSPICE software tool. The effect of process corners on read and write access time have been studied. N-curve method is used to analyze the static stability and stability parameters like SINM, SVNM, WTI and WTV have been measured and the effect of variation of power supply and temperature on stability have been studied .