STATIC LOW-POWER VERIFICATION OF SYSTEM-ON-CHIP (SoC)

Abstract

As technology nodes shrink to nanometers, the semiconductor sector is drastically scaling down. Processors are decreasing in size while increasing in performance and decreasing in delay. Power, performance, and area are the three primary considerations in the digital design of any processor or System-On-Chip. A good design is typically characterized by high performance and low power consumption, requiring less silicon area on the chip. All three criteria are interrelated, so if one improves, the other two will suffer as well. All throughout the world, scientists and engineers are attempting to improve all three elements simultaneously, which is pretty difficult. Today's integrated frameworks require low power architecture. The low power architecture is also essential for battery-powered applications, such as mobile phones, portable computers, pocket calculators, wrist watches and PDAs. Therefore, the necessity for low-power design and verification is urgent. Power management has risen to prominence in recent years especially in lower node technologies as static power dissipation is greater compared to dynamic power. In nanoscale technology, power dissipation will increase as the technological node decreases and the performance speed, number of transistors, and leakage current rise. Static power dissipation plays a vital role as the size of a technological node shrinks; therefore, this dissipation should be minimized in the design. Consequently, various Low power methods are presented in this report. Specialized power management cells that are UPF-compliant are also examined in depth. In this project, low power checks of SoC have been verified. Verification and debugging of low power checks has been performed through Low power verification tool which generates log files and report files. These files give error and warning messages in our iv design and help us to debug our design through graphical user interface mode to verify and eliminate errors. When Netlist, Unified Power format (UPF) and constraint files are given to a low power verification tool it generates log and report files. UPF is relatively a new concept which has been introduced in 2007, later it became IEEE 1801 Low Power Standards. While Netlist contains all information about functionality of design, UPF specify all power intent information in the design. This report comprises simulation results and reports of low power checks, which include all errors, warnings or violations, in order to comprehend all phases and procedures of static low power verification of SoC.