BLOCK LEVEL TIMING AND POWER OPTIMIZATION OF VLSI PHYSICAL DESIGN

Abstract

This project analysed and implemented VLSI physical design for CMOS technology, which is an important step towards fabrication of an integrated circuit on a silicon wafer. The physical design is performed in two levels, PNR Flow and ECO Flow. At ECO (Engineering Change Order) timing violations are fixed. There may be constraints that were missed on specific nets. ECO is used to control the timing behaviour of the design. The advancements in current day CMOS technology have resulted in shrinking feature size of the MOS devices and an increase in the potential packing density. This has enabled designers to offer increased computational powers to the end users on smaller and smaller devices which have resulted in a huge demand for portable devices such as PDAs, cellular phones, etc. But this trend in increasing logic complexities on a single chip has come with its own challenges. Apart from packing large functionalities on a single IC, consumer applications need to be designed to consume less power to reduce the package costs without compromising on the performance. The results obtained indicated that design optimization times can be significantly reduced by enabling concurrent optimizations in all the important PVT corners for the design under consideration. Tools are used for better optimization of design, to see run-time, and better QoR results. This helped in closing the design with minimal timing and other electrical violations in a shorter time when compared to the earlier trend of having a sequential optimization cycle. These aspects make it possible to leverage the capabilities of present day EDA tools to tape-out complex SoC designs in a competitive semiconductor market. Here we used the tool ICC compiler, Primetime, Calibre, Formality, and Redhawk.