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Title: | ANALYSIS OF VDDDA BASED VOLTAGE-MODE MISO AND SIMO UNIVERSAL FILTER |
Authors: | GOEL, DHRUV |
Keywords: | VDDDA VOLTAGE-MODE MISO SIMO UNIVERSAL FILTER |
Issue Date: | Aug-2020 |
Series/Report no.: | TD-5918; |
Abstract: | Research on analog signal processing has been heavily explored in the analysis and applications of various active building blocks (ABBs), which are expected to perform better than traditional op amps. Voltage Differencing Differential Difference Amplifier (VDDDA) is one such new versatile ‘voltage differencing’ active building block (ABB). It is a universal block to realize various amplifiers with less transistor count. Device’s internal structure consists of operational transconductance amplifier (OTA) followed by differential difference amplifier (DDA). In this project, two second order voltage-mode filters are proposed using the VDDDA as an active block. The first proposed filter is sort of MISO multifunction filter having three input nodes and single output node. It consists of one VDDDA, one resistor and two identical capacitors. The proposed filter can provide five standard functions: Low-Pass (LP), High-Pass (HP), Band-Pass (BP), Band-Stop (BS) and All-Pass (AP) responses for the same circuit topology. The natural frequency and quality factor both can be electronically controllable and tuneable. The second proposed filter is universal voltage-mode SIMO filter. It comprises of three VDDDAs, two grounded capacitors and single grounded resistor. The input voltage node exhibits high impedance. The proposed filter simultaneously provides Low-Pass (LP), High Pass (HP), Band-Pass (BP), Band-Reject (BR) and All-Pass (AP) responses with same circuit topology. The natural frequency and quality factor can be tuned electronically and orthogonally by dc bias current. The impedance at output nodes HP, AP and BR has low impedance which can connect to other circuit without the use of voltage buffer. This makes the proposed filter suitable for IC development. The theoretical results are verified by SYMICA DE simulations using TSMC 0.18µm SCN018 CMOS process parameters with ±0.9V supply voltages. |
URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/19358 |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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DHRUV GOEL M.tech.pdf | 1.34 MB | Adobe PDF | View/Open |
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