HIGH PERFERMENCE ENERGY EFFICIENT CMOS VOLTAGE LEVEL SHIFTERS

Abstract

In today's ICs and SOCs, voltage level Shifter (VLS) circuits are commonly employed as interfaces for several voltage domains (SOCs). The major design considerations for high performance level shifters are low power dissipation and low latency. In this dissertation we propose two voltage level shifter designs. The first being, an energy efficient voltage CMOS voltage level shifter. The main purpose of this voltage level shifter is to convert the voltage level from one level to another. We verified our voltage level shifter in ASAP7 7nm Fin Fet technology. The proposed voltage level shifter is based on differential cascade voltage switch logic, which takes an input voltage in the range of 0.25V to 0.6V and provides an output of 0.7V. Our voltage level shifter improves propagation delay and power dissipation with 48% and 43%, respectively, with recently reported Wilson current mirror voltage level shifter with zero-Vth design. The proposed design technique comes up with significantly lower power consumption and drastically reduced propagation delay over a wide range of temperatures (-25 to 25 degree Celsius), as compared to existing technologies. The secondly proposed design is based on select signal (Vin) voltage switch logic, which takes an input voltage in the range of 0.3V to 0.6V and provides an output pulse of 1.2 to 0.6V peak to peak. We verified our voltage level shifter in ASAP7 7nm Fin-Fet technology. Our voltage level shifter improves propagation delay and power dissipation with 42.76% and 39.6% respectively with recently reported Wilson current mirror voltage level shifter with Zero-Vt design. The proposed design topology comes up with significantly lower power consumption and drastically reduced propagation delay.