IMPLEMENTATION OF DIGITAL MODULATIONS ASK, PSK AND FSK IN VERILOG USING VEDIC MULTIPLIERS

Abstract

India, the sacred land of deep cultural heritage, has long demonstrated the efficacy of mathematics by introducing a faster and more efficient method of obtaining mathematical results through the innovative ideas of ancient vedic mathematics. It enables us to answer nearly all mathematical problems in much less time. Every fraction of a second counts in today's competitive environment to stay ahead. Modulation technique used in various communications over the radio carrier, is crucial to any of the wireless communication systems. The significant portion of wireless transmissions are digital today, and due to the limited bandwidth available, the encoding type is more essential than ever. The basic purpose of modulation today is to incorporate as much information as possible into the smallest bandwidth. The spectral efficiency goal examines how rapidly data may be transferred within the particular available bandwidth. To achieve and enhance spectral bandwidth efficiency, a variety of strategies have evolved. This dissertation intends to serve as a bridge between modern day digital modulations and the ancient Indian vedic mathematics. An extensive work has been done to implement a 32-bit vedic multiplier using the most efficient sutra (algorithm) called Urdhva Triyakbhyam. A Verilog code for generating sinusoidal signals had been written using a technique called Direct Digital Synthesis and by using these the present-day digital modulations namely Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK) and Phase Shift Keying (PSK) are built. This work is carried out in Xilinx vivado simulation software. An idea to implement modulation schemes using vedic multiplier and sinusoidal waveforms in Xilinx software with Verilog coding has been implemented. The implemented BASK proved impressive in the amount of total on chip power consumption. The power results obtained from Xilinx power report are furnished herewith.