DESIGN AND ANALYSIS OF LOW POWER SRAM

Abstract

In the present scenario the portable operated battery devices has significant demand in low power IC design. In modern SOCs, embedded SRAM has an important part and traditional SRAM designs are not good in performance and also consume more power. In this project the working of SRAM has been discussed, and analyzed the power consumption by the static random access memory (SRAM). There are different strategies to reduce the different power loss in memory cell, but here our main focus on to reduce the leakage power. Because the transistors are growing in SRAM unit, it leads to increase the leakage current. Now transistors are scaling down it made leakage current more crucial in term of power loss. So reduce the power loss from the memory cell stacked technique has been used. In stacked technique N type transistor is used. In this technique the NMOS transistor is placed in between the cell and ground. First analysis has done with only one transistor and second time the analysis has done with the help of two NMOS transistor. After that a comparison has been done among traditional 6T SRAM cell and proposed design of low power SRAM cell. The stacked designed techniques-based SRAM cell has better performance with respect to power consumption compare to traditional SRAM cell.