LOW POWER LOW NOISE PLL DESIGN

Abstract

Traditionally, the PLL has been a linear circuit. While the first PLLs were built with discrete components, they were made available in discrete ICs across 1965. Each of these was linear devices (LPLLs), which were constructed through semiconductor technologies similar to the operational amplifiers of the time. A few years later (around 1970s), the first digital PLLs (DPLLs) became available, however when we look at their schematics, we could see that only the phase detector was built from logic, while the VCO and loop filter remained analog. As a consequence, PLL can be considered of as a hybrid system. Furthermore, we integrate LPLLs and DPLLs into a single class known as mixed signal PLLs. A PLL is a very versatile device that can be found in most of the devices we use every day. Since its inception, it has been constantly evolving and implemented in various technologies a, whereas the basic phase look loop circuit hasn't changed.. The PLL circuit is broadly utilized communication systems, including, mobile phones, radio, telephone personal computers and electronic devices. PLLs oftenly finds its uses in mobile or wireless communications for synchronization, clock synthesis, and jitter reduction. A PLL used in a microprocessor to generate clocks appears to be very similar to a frequency synthesizer used in a cell phone, but the actual circuits are designed very different manner. This report describes the design and the basic concepts of the PLL, along with its operation principle and block diagram, have indeed been explained first. This is based on a detailed explanation and stability analysis of individual blocks in the PLL, which uses negative feedback to achieve phase/frequency lock. Ltspice is used for the design and implementation, and 90nm technology was used. Simulations of each individual block were described to further explain the function of each individual block, such as the Phase Frequency Detector (PFD), charge pump, Low pass filter (LPF), and Current Starved Voltage controlled Oscillator (CSVCO), as well as the calculation of performance measures such as capture range, lock range, and settling time. Finally the simulation for the complete PLL has been presented along with the calculation of its performance metrics like capture range, lock range and settling time.