DESIGN AND IMPLEMENTATION OF OPTIMISED MAGNITUDE COMPARATOR USING DIFFERENT LOGIC STYLES

Abstract

With the semiconductor industry scaling down to the nanoscale regime, the three factors come hand in hand that are namely the speed, power and the area. These three factors are inter-relatable and furthermore the power is classified as power consumed and the power dissipated. As we reduce the size of the Integrated Circuits (ICs), the power consumed by the circuit should also be reduced, and at the same time some effects become prominent at the nanoscale and therefore need to be considered. At the nanoscale, as these effects became prominent, this led to the modification in the structure of the devices to be used for the low power applications. Moore’s law has been the backbone of the VLSI industry which says that the transistors on the chip doubles every eighteen months and this has been followed up till now. The designing of the devices and the circuits on the EDA tools provided by the industry reduces the cost of manufacturing by a large scale as the fabrication of the devices is costly process. In the advanced technology low power, speed and size play a significant role specifically in the field of magnitude VLSI circuits. 2-Bit magnitude comparator design using different logic style is proposed in the brief. Comparison is the most basic arithmetic operation that determines if one number is greater than, equal to or less than the other number. The main objective of this project is to design and implement of magnitude comparator using different logic techniques and compared in terms of power v consumption, propagation delay and transistor count in cadence virtuoso 90nm technology file.