DEBUG CONTROLLER VERIFICATION OFA GRAPHICS CHIP

Abstract

Verification is considered a critical stage of any chip development cycle. This step ensures that the design meets the system requirements and specifications. At this stage, test cases are developed, and the invention's functionality is checked. But it is supposed that Verification takes almost 60% of the total chip development chip cycle. It makes it a critical stage in any chip flow since any bug found post routing is a bit tough to remove, and also, post-fabrication, it is challenging to correct the design. The project focus on improving the efficiency of verification cycle. It can be achieved by introducing a Debug Checker in the Testbench itself, which reduces verification time many folds. The project targets segregating the potential bug region once any mismatch or error is found in Testbench.